1. Field of the Invention
The present invention relates in general to a circuit for controlling a self refresh operation of a memory cell array, and more particularly to a self refresh control circuit for the memory cell array which is capable of adjusting variably a self refresh period of the memory cell array according to a temperature variation in a chip to reduce an amount of current required to hold data stored in the memory cell array.
2. Description of the Prior Art
Generally, a dynamic memory device comprises a plurality of memory cells and an amount of charge stored on a capacitor of each memory cell is reduced due to a leakage with the lapse of time. For this reason, a refresh operation is periodically performed to recover the leakage charge amount on the capacitor. If a refresh period is too long, the leakage charge amount on the capacitor becomes large, thereby making it impossible to discriminate whether data stored in the memory cell is "1" or "0" in logic. Here, a critical time required to 11old the data stored in the memory cell in the refresh interval is called a data hold time. The refresh operation is performed at a desired period to hold the data stored in the memory cell, which is called as a self refresh (SR) operation. The self refresh operation is performed in a self refresh mode. Noticeably, a self refresh period must be set to refresh all the memory cells in the dynamic memory device at least once in the data hold time.
FIG. 1 is a graph illustrating a general relationship between the data hold time and the self refresh period based on a temperature variation. As an ambient temperature rises, the leakage charge amount on the capacitor is increased, thereby causing the data hold time to be shortened. Namely, as shown in FIG. 1, the self refresh period is constant regardless of the variation of the ambient temperature, whereas the data hold time becomes gradually short as the ambient temperature rises. For this reason, the self refresh period must be determined by way of precaution against the worst condition or the very high temperature.
However, in the case where the self refresh period is set by way of precaution against the worst condition, the self refresh operation is performed excessively frequently when the ambient temperature is normal, resulting in an unnecessary loss in an amount of current. For this reason, in order to prevent the unnecessary loss in the current amount due to the self refresh operation, it is necessary to adjust the self refresh period according to a variation in the data hold time with the temperature variation.
FIG. 2 is a graph illustrating an ideal relationship between the data hold time and the self refresh period based on the temperature variation. From this drawing, it can be seen that the self refresh period must be adjusted to be long in the case where the data hold time is long at a low temperature. Also, in the case where the data hold time is short at a high temperature, the self refresh period must be adjusted to be short. In FIG. 2, the reference numerals M and M' designate margins between the data hold time and the self refresh period at the high and low temperatures, respectively. As seen from FIG. 2, the margins M and M' at the high and low temperatures are substantially the same, namely, M.apprxeq.M'.
In order to solve the above problem, a conventional self refresh control circuit comprises a temperature compensation circuit to generate a self refresh request signal at a shorter period at the high temperature, whereas at a longer period at the low temperature, so as to reduce power consumption in the self refresh mode.
However, such a conventional self refresh control circuit has a disadvantage in that a temperature variation of a memory cell array in the memory device cannot accurately be compensated because a temperature sensor is disposed in the outside of the memory device. Also, the temperature variation of the memory cell array cannot accurately be compensated since temperatures sensed by the temperature sensor are classified into only two regions, high and low temperatures. Further, timers are operated at periods different according to the temperature regions, resulting in an increase in the power consumption and an increase in a layout area.